HW & SW design of the AXI Quad SPI IP core

hfwang132@gmail.com (hfwang132) — Sat, 01 Jul 2023 17:49:31 +0800

1 Basics

SPI has three-wire mode and four-wire mode. The three-wire mode consists of three wires - SS (Slave Select), SCK (SPI Clock), and MOSI (Master-In-Slave-Out). The four wire mode has an extra line called MISO (Master-In-Slave-Out).

Signals	Full Name
SS	Slave Select
SCK	SPI Clock
MOSI	Master-Out-Slave-In
MISO	Master-In-Slave-Out

SPI clock has four modes: CPOL=0/1 and CPHA=0/1. CPOL stands for clock polarity – clock low or high when in idle. CPHA stands for clock phase – data valid at 0 degree or 180 degrees.

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HW & SW design of the AXI Quad SPI IP core

1 Basics